ORSoC offers professional support for OpenCores technology.

For commercial companies it is important to know that there is professional support available when you choose technology for your next product.

The OpenCores technology is free (as open source) and highly popular. Additionally you can be sure that support is available from professional design experts. ORSoC offers all kind design and verification services, from evaluation of a specific IP to total SoC design including OS (i.e. Linux).

ORSoC has a unique knowledge of designs based of the OpenCores technology. The technology can be described as a generic platform based on Open Source IP with the OpenRISC processor as a centralized IP block. All IPs are open source meaning there are no license fees related to their use.

The technology enables ORSoC to develop customer specific systems faster and much more cost efficient then our competitors.

The Open Source technology gives the customers the following benefits:

• No processor license fees: This provides the customer with the most cost efficient solution available, and there are no restrictions on how to use the processor

• Access to the source code of all IP’s: Give the customer full control of the design and are not locked to any vendor or fab

• Technology independent: The design can easily be ported between different technologies (FPGAs, Structured ASICs, Standard ASICs)

• Flexible design: Since the customer have access to the source code it’s fully possible to add/modify/reuse the design

ORSoC are specialized in designing hardware systems using the OpenRISC processor (OR1200). The OpenRISC OR1200 processor is a high-performance 32-bit RISC processor. It is license and royalty free.

Internal units include Harvard cache architecture (8KB+8KB), TLB based MMU to provide virtual memory, debug unit, timer unit, DSP MAC, 32-input interrupt controller and power management.

OR1200 is very suitable for embedded, portable and networking applications, regardless of the target technology. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system. Competitors include ARM10, ARC and Tensilica RISC processors.

The figure below shows the general architecture of OR1200 IP core. It consists of several building blocks:
• CPU/DSP central block
• Direct-mapped data cache
• Direct-mapped instruction cache
• Data MMU based on hash based DTLB
• Instruction MMU based on hash based ITLB
• Power management unit and power management interface
• Tick timer
• Debug unit and development interface
• interrupt controller and interrupt interface

When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. The default OR1200 configuration uses approximately 1M transistors.