2010-08-11
ORSoC employs Martin Wasielewski

ORSoC has employed Martin Wasielewski to our Stockholm office. Martin has +10 years experience in the field of FPGA/ASIC development. Martin has also worked with design architecture issues and hardware systemisation. We are very glad to have Martin in our team.

For more information about available resources, please contact Johan Rilegård: +47 70 824 80 30

2010-08-05
Meet us at the FPGA World conference in Kista, September 8th 2010

ORSoC will have a booth at the exhibition and will do a cool product presentation at 13.00.

Product presentation:
OpenRISC processor based embedded SoC platform, running Linux - 100% Open Source!

The presentation will give you a hands-on demonstration of a system-on-chip design including OpenRISC processor, Ethernet and USB functions, running Linux 2.6.34 with Busybox 1.17.0. The system offers endless possibilities to optimize the design, based on your specific requirements, and provides full visibility during debugging compared to other commercial black-box-solutions.

See you there.

For more information, please contact Johan Rilegård: +47 70 824 80 30

2010-08-02
ORSoC employs Olof Kindgren

ORSoC has employed Olof Kindgren. Olof is a very skilled FPGA & ASIC developer with many years experience. Olof is located in Gothenburg and will even further improve our presents in the west regions of Sweden. We are very glad to have Olof in our team.

For more information about available resources, please contact Johan Rilegård: +47 70 824 80 30

2010-05-27
Update of existing product gives increased performance and lower cost

ORSoC will help one of our customers to update their existing products. The design changes will give improved functionality and increased performance. We will also be able to make the product more optimized which will give a significant cost reduction.

The project is a quite short (less than one month) and it is good to see that a fairly small work effort give a great impact of the product.

For more information, please contact Johan Rilegård: +47 70 824 80 30

2010-03-08
ORSoC design a large OpenRISC based SoC design, running Linux.

We will help our customer to design a large SoC design including the OR1200 processors and several peripherals IPs from OpenCores, such as USB, Ethernet, CAN, SPI, I2C, SD-card, etc

The product will be running the latest Linux distribution and is designed to act in a high critical environment.
It is also important that the product have low power consumption.

This is a very interesting project and suits ORSoC perfect, thanks to our SoC design/verification expertise as well as our experience of using the OpenCores technology.

For more information, please contact Johan Rilegård: +47 70 824 80 30

2010-01-22
ORSoC employs Tor Caesar

ORSoC has employed Tor Caesar - a senior FPGA & ASIC developer who has worked within this technical field over 20 years. Tor has worked with products targeted for several different industries and applications, with focus on the telecom sector. With his unique expert knowledge and extensive experience within verification (Specman), Tor has a perfect profile for our customer looking for expert services within FPGA/ASIC development. We are very glad to have Tor in our team.

For more information about available resources, please contact Johan Rilegård: +47 70 824 80 30

2009-09-01
Live demo of an OpenRISC processor SoC - FPGAWorld, Kista 10th of September 2009

ORSoC will participate in the FPGAWorld conference in Kista, the 10th of September 2009. We will present a “live demo of an OpenRISC processor SoC, running Linux, showing the great possibilities of an Open-source system. A guaranteed Powerpoint free session”.

ORSoC will be present with a booth at the conference and, as always, we are looking forward to meet many interesting customers, colleague and competitors.

We will be glad to discuss our expertise in System On Chip design, including FPGA/ASIC development, as well as how you can benefit form using open source IP cores from OpenCores in your next design.

For more information, please contact Johan Rilegård: +47 70 824 80 30

2009-08-03
ORSoC enter into a new big conversion project.

We will help our customer to retargeting a big SoC design from a Xilinx FPGA into an Altera device, for further conversion into a gate array ASIC. ORsoC will do all the work of this conversion, including:

• Conversion of the existing Xilinx VHDL design to an Altera FPGA.

• Modification of technology specific parts of the current design (memory, I/O, etc)

• Frontend design (modification of RTL design for top level, I/O ring design)

• Backend design (synthesis, placement, routing, layout, timing)

• Verification

• Project management

The project has a very thigh time schedule and ORSoC has undertaken the whole responsibility.
We are sure this will be a successful project. ORSoC has huge expertise and experience from this kind of work from over 30 FPGA/ASIC conversions.

For more information, please contact Johan Rilegård: +47 70 824 80 30

2009-05-12
ORSoC employs Krister Karlsson

ORSoC continue growing and increase our team with even more senior resources within FPGA and ASIC design, by employing Krister Karlsson. With over 15 years in the ASIC business, Krister has deep skills and extensive experience in ASIC and DSP development and has developed products targeting several industries, i.e. Chip architecture for network processors, Multiprocessor architectures with application specific DSP, Processor based digital systems for multimedia applications. We are very glad to have Krister in our team.

For more information about available resources, please contact Johan Rilegård: +47 70 824 80 30

2009-04-15
OpenRISC Development Kit

ORSoC has designed a development kit for the OpenRISC processor. This kit enables easy access to the OpenRISC platform and gives the designer a fast start.

The development kit includes the following:

• FPGA (CPU) board: The board is shipped with a pre-defined System on Chip design and includes everything to have a CPU system up and running in no time.

• I/O board: This is a companion board to the FPGA board. The boards may be mounted together via fixed-connectors. The I/O board contains several IOs useful for development of many different products/applications i.e. Ethernet, USB, Audio, GPIO, GPs, etc.

• JTAG-USB debugger: The USB to JTAG debugger is aimed at debugging OpenRISC based systems. One or more OpenRISC processors can be controlled over a JTAG interface by easy connection to a USB host. A local proxy server handles the USB connection and offers a TCP connection to a software debugger.

• VMware-image for easy start, including tool-chain and simulation.

More information is available at the “Development Kit” page.
--"Development Kit" page--

2009-03-13
OpenCores – release a brand new website! (press release)

We are very glad to finally present the new website of OpenCores (www.opencores.org)

During the last couple of months ORSoC (maintainer of OpenCores) has completely re-designed the OpenCores website – primarily concerning the technology/platform but also including some layout upgrades. The new platform provides much greater flexibility and enables us to continuously add new features.

Marcus Erlandsson, CTO at ORSoC has been responsible for the upgrade work and describes the news:
The first thing you will notice when visiting the new OpenCores is a new design and logo, but soon you realize that the big improvements are within the services supported by OpenCores, they include:
- The CVS has been replaced with SVN (Subversion is a more modern/better revision control system).
- The Forum has been replaced giving a better overview making it easier to follow the discussions within different “threads”.
- Statistic improvements - we can now present much better statistical information from all the activities within the community. This includes real time statistics of the overall visitors/users experience as well as statistics for all projects available at OpenCores.

OpenCores is continually growing; more and more companies and engineers visit the site and use the cores as well as discussing design and verification solutions at the forum. Therefore this update was timely and we are very glad to now have a platform which can support all the users and also handle all the future services we will add to the site/community.
The work load to build the new site has been huge, due to the large number of users together with over 600 projects in the repository. Now we have released the new site we will continue to add more functionality that will make it even easier for engineers to develop and distribute open source hardware IP cores on OpenCores.

We hope all users, advertisers and partners will be pleased with the updated version of site and that we soon will be back with more news regarding OpenCores and the services attached to it, says Johan Rilegård CEO at ORSoC.
Enjoy, OpenCores and ORSoC

2009-02-23
Product update - New I/O-board available

ORSoC has designed a companion board to the FPGA development board. The boards may be mounted together via fixed-connectors. Intended use is to build Ethernet connected products.

The board has the following functions:

• four independent Fast Ethernet ports with RJ45 connectors

• serial port with PPS input to be used with GPS receiver

• two independent USB host with USB type A connectors

• AC'97 compatible audio codec with mic, line in and line out. 3.5mm jack

• SD / SDIO connector

• 4 analog in channels

• 8 general purpose digital IO

• high intensity RGB LED

• RC5 compatible IR receiver

The board is 100x100 mm and is supplied from the USB port on your computer or from a USB hub.

More information is available at the “I/O board” page. --"I/O board" page--

2009-02-05
ORSoC employs Magnus Anehem

ORSoC increase our resources within FPGA and ASIC development, by employing Magnus Anehem. With over 15 years in the ASIC business, Magnus has deep skills and extensive experience in FPGA- and ASIC development. Magnus has mainly worked in projects targeting the telecom industries – including Bluetooth communication and application processor ASIC’s for mobile phones. We are very glad to have Magnus in our team.

For more information about available resources, please contact Johan Rilegård: +47 70 824 80 30

2009-01-15
ORSoC and AsiusTech form strategic partnership (press release)
With the background of strong personal cooperation in the past, ORSoC and AsiusTech have decided to form an official partnership combining open source IP technology (from OpenCores) with cost optimization to create a cost effective design technology service.

The expertise within ORSoC and AsiusTech complement each other extremely well. ORSoC has unique expertise within SoC design, including FPGA and ASIC development, based on open source IP cores. AsiusTech has extensive experience in the area of product cost optimization.

ORSoC is established as the number one company working with open source IP cores in FPGA and ASIC design, which gives huge benefits during the entire product life cycle – cost, life time, vendor independency, etc.

AsiusTech will contribute with its expertise in cost optimization processes and strong experience of analysis, design and manufacturing of electronics products.

The partnership is aimed at demonstrating the joint forces of the companies to the market and also enables effective project resources to be allocated for our customers.

“There is a huge interest of using open source alternatives right now. Cost reduction is one important aspect, but even more important is the independence of specific components/vendors to assure the cost optimization during the entire product life cycle. Together with AsiusTech we can offer the customer a wider scope and optimize the total product cost and the process for manufacturing. This partnership is expected to result in a very positive outcome for our customers”, says Johan Rilegård, ORSoC.

“When looking for cost effective ASIC & FPGA technologies, we find the cooperation with ORSoC to be an outstanding partnership for us. We expect that our customers want the increased vendor independency, legacy CPU support for processors near end-of-life and short implementation time”, says Håkan Dahlbom, AsiusTech.

About AsiusTech (www.asiustech.com)
AsiusTech has a long experience of Value Engineering from within one of the major EMS companies in the world. The company offers an electronics design portfolio with product cost optimization as a specialist service. With a background ranging from high volume products and cost reduction studies, to everything from telecom infrastructure and consumer products, AsiusTech help customers to increase or maintain their margins.

For more information, please contact:
Johan Rilegård, CEO ORSoC at +46 70 824 80 30
Håkan Dahlbom, CEO Asius Hardware Technology AB at +46 733 67 5118,

2008-10-27
OpenCores now has more than 20,000 registered users! (press release)
OpenCores can now proudly announce that we have more than 20,000 registered users. This makes OpenCores the largest community of its kind. The OpenCores website, www.opencores.org, is regularly visited by around 70,000 engineers every month with every one helping to contribute to the development and verification of the new and existing IP cores.

We are extremely proud and excited about the great interest shown for open source hardware IP cores.
The number of newly registered users is continuously increasing by approximately 200 users per day. This means we will have over 50,000 registered users within the next 6 months. This gives OpenCores a unique possibility to generate statistics which will be used to further increase the quality of the IP-cores.

It's very interesting to see the mix of users within OpenCores. There are FPGA and ASIC developers with many years of experience as well as users from all the big universities. It is quiet fun to present the number of years of experience that are visiting OpenCores every month. If we summarize the experience from all visitors of one month we see that OpenCores is visited by: ~236 000 years experience of FPGA development, ~112 000 years experience of ASIC development ~147 000 years experience of Verification

During the summer OpenCores began developing a new website which will give us the possibility to add many new features. The site will be launched sometime in November and will, from the start, be quite similar to the existing site. The exception being the forum which has had a facelift to improve functionality. This improved functionality will allow us to present improved statics in a more automated format.

OpenCores:
OpenCores is the world’s largest site/community focusing on open source hardware IP cores development. OpenCores source over 550 different IP cores, including processors, peripherals, crypto cores, etc. OpenCores was established back in 1999 and during the last few years the cores have become extremely popular among both big and small companies, thanks to its very clear advantages. OpenCores is owned and maintained by ORSoC, Swedish design house experts in SoC development based on OpenCores technology.

For more information, please contact Johan Rilegård at +46 70 824 80 30

2008-08-25
ORSoC and OpenCores is the headline at Elektroniktidningen
In the August edition of Elektroniktidningen (one of the biggest Nordic magazines within the electronic business) had a big article about ORSoC and OpenCores. Please read the article here.
You can also read the whole magazine here.
Enjoy!

2008-08-19
Meet us at the FPGAworld conference the 9th and 11th of September
ORSoC will attend to the FPGAworld conference. The conference will take place at Electrum Kista in Stockholm Sweden on September 11 and at Ideon Lund on September 9.
ORSoC will present 3 different presentations.
1) Industrial presentation covering the evaluation of open source within hardware. Using open source cores within SoC design has become very popular the last couple of year and we will during the present discuss the key component behind this highly increased interest.
2) Product presentation EDA-tool. By using ORSoC custom developed EDA-tool (called ISoC) we can put together a SoC design in a very short time. We will during 30 minutes show you this tool and put together a real design.
3) Product presentation eASIC: We will present eASIC's Nextreme Series which is a new generation of ASIC devices with zero mask charge, that dramatically reduce the cost and risk of doing ASIC design.
Please visit the FPGAworld website (www.fpgaworld.com/conference) to check out the presentation program and registration (the conference and exhibition free).
In Stockholm we will also have a both in the exhibition hall. We look forward to meet you there. /The ORSoC team.

2008-08-11
eASIC announce 45nm Structured ASIC with zero mask charges
Nextreme-2 is a family of zero mask-charge NEW ASIC devices, manufactured on a 45nm CMOS process, and built using eASIC’s patented single-via customization technology. The Nextreme-2 family provides ASIC-like performance, power and low unit-cost combined with FPGA-like design flow and rapid delivery of devices. Nextreme-2 is built on a breakthrough configurable fabric which combines efficient Look-Up-Table (LUT) based logic with single via-layer customized interconnect. Nextreme-2 delivers many enhancements and advantages for designers considering standard cell ASICs, FPGAs and ASSPs. More information is available at the “eASIC” page.
--"eASIC" page--

2008-07-17
Complete SoC development environment now available at OpenCores
OpenCores is pleased to announce the release of a solution aimed at lowering the technical threshold of development with the open-source OpenRISC processor.

There will always be barriers to overcome when changing to a different processor architecture. OpenCores now offers its flagship LGPL licensed 32-bit RISC processor along with a pre-configured design environment to make these problems easier to solve. Using a virtual machine pre-configured with the necessary tools, it is now even simpler to start integrating proprietary IP, or license-fee free IP from OpenCores, with the world's most used open-source processor, the OpenRISC 1200.

OpenCores has made available a "Virtual Ubuntu Linux" installation which installs and configures a VMWare virtual machine. It includes all of the tools necessary to start hardware and software development on a OpenRISC platform.

It provides an OpenRISC SoC reference design along with the following development tools:

• Icarus Verilog simulator

• GTKWave waveform viewer

• Software tool-chain based on gcc-4.2.2 with uClibc-0.9.29

• Support for Busybox-1.7.5 and Linux-2.6.19

• The OpenRISC architectural simulator

This package provides simplicity, ease of use, and is a great leap forward for developers who decide to base their designs on OpenCores IP.
This release is available at: http://www.opencores.org/projects.cgi/web/or1k/vmware_image
For further information, please contact Marcus erlandsson by email: marcus.erlandsson[at]orsoc.se or by phone: +46 70 824 80 33.

2008-06-18
OpenCores has reach over 500 existing projects (IP-blocks).
A huge amount of new projects have started at OpenCores during the last 9 month, from about 400 projects in mid 2007 up to over 500 projects today! The same positive trend is shown in the number visitors to the site.

Among the new projects there seams to be some really interested ones which probably will be highly downloaded and used.

OpenCores has started to improve the site with new features/functionality for the purpose of increase the statistics and feedback from users of different IPs. This is important in our work of supporting the world with well-developed and well verified open source IPs with. Allot of feedback has come into the community and (more or less) everyone see the positive outcome from the improvement. - If everything goes as planed we will be able to present more positive news related to new functions within shortly. Our mission is to support all developers and users of open source IPs with the best possible community for theirs projects.

OpenCores is the world’s largest site/community for development of hardware IPs as open source. The site holds all the IPs and makes them available for everyone to download, use and improve. OpenCores is also a source of information and forums related to IP- & SoC-development.

2008-04-28
ORSoC increase with new interesting customer
ORSoC got many request for design services. The major part of our new projects includes designs based on OpenCores IPs. ORSoC continue to work with our existing customers, but have during the last nine month extended our customer base with a number of new, very interesting, customers. The customers act within different industries and they are all developing complex products in extremely competitive markets.

2008-03-28
FPGA & ASIC developer wanted
ORSoC is seeking more strong candidates who are experienced in FPGA or ASIC design. Please check out the current vacation page for more details.
--"Current vacancies" page--

2008-02-26
ORSoC release a new ASSP
ORC32-1208 is an OpenRISC based System-on-Chip implementation. The design suits into many different applications. It is a highly integrated design with a large number of built-in peripherals. More information about the product, including datasheet is available at the “ASSP” page.
--"ASSP" page--

2008-02-20
OpenCores grows more than ever
A huge amount of new projects have started at OpenCores during the last 4 month, from about 400 projects up to 469 projects today! The same positive trend is shown in the number of registered users. Among the new projects there seams to be some really interested ones which probably will be highly downloaded and used.

2007-12-03
New development board
ORSoC has designed a development board for the OpenRISC processor. This board enables easy access to the OpenRISC platform and gives the designer a fast start. The board includes everything to have a CPU system up and running in no time. More information about the product, including datasheet is available at the “FPGA Development board” page.
--"FPGA Development board" page--

2007-11-19

ORSoC is the new partner for OpenCores

From the 1st of November opencores (www.opencores.org) will be maintained by ORSoC.

For a long period of time ORSoC has worked closely to OpenCores, both with the community and with development of the technology. The great benefits of open source IPs have been clearly proven in several projects. There has also been an explosive development in the interest and use of the technology during the last couple of years.

The great interest of OpenCores proves the importance of the site and its “philosophy” – to develop and provide the technology-world with free, open source hardware IPs. To ensure the continuing growth of the site/community ORSoC has decided to accept the mission to maintain and develop OpenCores.

ORSoC will continue to develop and improve OpenCores. We will dedicate resources to work with the site/community which will ensure that the development of IPs will ramp up and the quality of projects and verification will become even higher. In the long term we will also improve the web-site, to make sure it will offer even more services and make it easier for all the skilled engineers to work with IPs at the OpenCores.

ORSoC would like to see cooperation with different companies to create a turbo effect regarding the IP development. We believe there are many companies out there with in-house developed IPs - IPs that is not customer specific and which not is unique for the specific company. If these IPs are placed at OpenCores the IPs will continue to develop and they will be well verified.

ORSoC will also offer companies the possibility to advertise at opencores.org. This will provide an income to enable the site to develop and expand. Opencores.org is visited by millions of engineers from all over the world. Therefore the possibility to advertise at the site is mainly aimed for international companies. We believe that opencores.org is the best available marketplace for offering products/tools/services at the electronic development market.

We have the vision of continued development and improvement of OpenCores – the worlds largest site/community within open source hardware IPs. We hope that all developers and users will continue to contribute to the future of OpenCores.

For more information, please contact Johan Rilegård at +46 70 824 80 30.

2007-11-05
Career
ORSoC is looking for talented, new co-workers. Please feel free to e-mail your application.
Job Openings:

• ASIC developer, both with design- and verification expertise. Experience from Specman is positive. Location: Stockholm
• FPGA developer, with deep knowledge and experience in VHDL/Verilog based SoC designs. Location: Stockholm and Västerås.

Please observe that there is an absolute requirement that you speak fluent Swedish and English. For more information and to apply, please contact Johan Rilegård by email: johan.rilegard[at]orsoc.se or by phone: +46 70 824 80 30.

2007-10-08
ORSoC employs Sven-Åke Andersson
We can gladly announce that Sven-Åke Andersson joined the ORSoC team. Sven has deep skills and extensive experience in FPGA- and ASIC development from over 30 years in the business. Sven is also well known from his blog “FPGA from scratch” www.fpgafromscratch.com - a very educating on-going tutorial of how to design with FPGAs from the ground up. We are very happy to have Sven in our team.

2007-09-11
FPGA- & ASIC developer wanted
ORSoC continues looking for skilled and experienced FPGA- and ASIC developers. Since we focus on expert services within this market it is important that you have deep skills and experience within the area. If you like to work in fast growing company with skilled people please contact us.
For further information please contact Johan Rilegård (+46 70 824 80 30)

2007-08-22
Loads of new projects
After an intensive summer we can establish the fact that the autumn will be full of new exiting projects combined with continuing and expanding existing projects. As usual we focus on expertise services within the area of FPGA and ASIC development.

2007-06-04
Huge interest for the OpenCores-technology
ORSoC notice a great interest about the OpenCores-technology among many different customers and partners. There has always been a huge interest for the technology thanks to all the benefits connected with OpenSource technology, and now the numbers of implementation increased. During the last 6 month we have done more designs including OpenCores IPs than we implemented during the last two year together. This is a direct effect of the proven positive effects that comes with the technology.

2007-04-16
Positive trends - Increased project flow
During the last year ORSoC has noticed a very positive response from the market. Our strategy to always offer our customer the best possible skills and knowledge within FPGA and ASIC development seams to be right, says Johan Rilegård. We do not want to be a resource consultant, it is important for our customer that we have deep skills within our area. The fact that we usually work with customer over long time in different projects, shows that we offer the right services.
For further information please contact Johan Rilegård (+46 70 824 80 30)

2007-02-19
ORSoC has a very positive growth rate and continue to expand the workforce.
ORSoC expand the workforce with more knowledge and resources. We are glad that we have had the privilege to find and attract very skilled engineers. ORSoC has a very positive growth rate and aim to employ even more people during the beginning of 2007. This will give us the opportunity to serve our existing and future customer in the best possible way, in the same time we can continue our internal development work of both technology and tools.
For further information please contact Johan Rilegård (+46 70 824 80 30)

2007-01-18
ORSoC can now offer the Nordic customers eASIC’s Nextreme product family with a soft ARM processor.
FPGA, ASIC and System-on-Chip designers can benefit from a low-cost, fast-turnaround design with no-minimum order quantity - now including the option of an ARM926EJ processor. This will enable a broad range of users to have access, for the first time, to a 32-bit CPU core on a configurable fabric, while meeting the power, price and performance requirements of their Structured ASIC or Platform Designs.

eASIC implemented the 32-bit ARM926EJ processor using its standard design flow and obtained 150MHz typical performance. The 90nm Nextreme family with the embedded ARM926EJ processor is available now and is well suited for use in a vast range of applications, including digital imaging, portable media players, wired communication, wireless communication, storage and industrial.

We are excited about this cooperation and are glad to offer such a unique product. It gives our customer a exceptional option to an already outstanding alternative in their work of finding cost- and performance effective alternatives to FPGAs, says Johan Rilegård, CEO ORSoC.
For further technical information please contact Marcus Erlandsson (+46 70 824 80 33)

2007-01-05
ORSoC and Flextronics sign a long term partnership agreement.
ORSoC and Flextronics Design sign a long term partnership agreement. ORSoC will support Flextronics with knowledge/recourses for SoC designs and FPGA/ASIC development.
- We are satisfied with the agreement and it will for sure be a very fruitful cooperation for both parties, says Johan Rilegård. Flextronics is a great partner to us as we both has the goal to find the ultimate technical solution for our customers.
For further information please contact Johan Rilegård (+46 70 824 80 30)

2006-12-18
ORSoC is looking for experienced FPGA developers.
ORSoC is looking for 2-3 skilled VHDL designers with experience in FPGA development. You will work primarily in customer projects including SoC design, FPGA development/redevelopment but the post might also include internal development work. If you have the right profile please contact us.
For further information please contact Johan Rilegård (+46 70 824 80 30)

2006-11-06
ORSoC expands the workforce.
Michael has a unique knowledge and experience in SoC development. He has worked with the OpenCores organization for a long time. -We are exited to have Michael in our team. With his overall experience in electronic development combined with his expertise within SoC designed based on OpenSource IPs, he will be a very important resource for ORSoC and our customers.
For further information please contact Johan Rilegård (+46 70 824 80 30).

2006-10-11
ORSoC and eASIC announce their cooperation. ORSoC are the Nordic rep (DSR) for eASICs unique semiconductor technology.

ORSoC and eASIC has worked together for about a year now. The official announce-ment was set to October 11, 2006. This partnership expands our service capability to our Nordic region customers who are eager to have such a low-cost, no NRE ASIC capability that can be rapidly shipped in any volume.

About eASIC
eASIC offers breakthrough Structured ASIC products called Programmable ASICs, including Configurable Logic IP, aimed at dramatically reducing the overall fabrication cost and time of customized, high-performance semiconductor chips. Its patented architecture enables rapid and low-cost ASIC and SoC (System-on-Chip) designs through innovative use of programmable logic technology coupled with single Via-layer customizable routing. With just one Via layer to customize, Direct-write e-Beam processing becomes possible at 10x the pace, thereby enabling eASIC to offer NRE-free Programmable ASIC devices. eASIC’s technology has been successfully proven in silicon and validated by world-class semiconductor vendors.
Founded in 1999, eASIC Corporation is a privately held company, headquartered in Santa Clara, California. Investors include Vinod Khosla, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, and Evergreen Partners. www.eASIC.com
For further information please contact Marcus Erlandsson (+46 70 824 80 33).

2006-09-15
ORSoC will attend to FPGAworld conference (November 16), in Kista, Stockholm.

ORSoC will present the benefits of designs based on the OpenCores technology. We will also present the eASIC technology. Please come and meet us in our booth at the exhibition and/or listen to us in the conference.
For further information please contact Johan Rilegård (+46 70 824 80 30).

2006-08-28
Customer project using the OpenRISC processor (OR1200). ORSoC redesign an ASIC using the OR1200 processor to optimize the design.
ORSoC is pleased to announce a project for a huge Swedish customer. The project is to redesign an ASIC that does not fit the product requirement. To optimize the performance and reduce cost the OpenRISC processor (OR1200) is used in the design.
For further information please contact Johan Rilegård (+46 70 824 80 30)