USB-JTAG DEBUGGER

ORSoC has developed a USB to JTAG debugger, aimed at debugging OpenRISC based systems. One or more OpenRISC processors can be controlled over a JTAG interface. Additionally the debugger could be used to handle a serial connection for a console. Signal level on the JTAG is user configurable by use of an external voltage.

The debugger is USB 1.1 compatible for easy connection to a host. A local proxy server handles the USB connection and offers a TCP connection to a software debugger. The GNU debugger with optional graphical user interface, such as DDD, is supported.

Connect to the design under test with a 10 pin ribbon header. Debugger uses a 2x5 pin header with 0,1" spacing. Use the following pinout:

1. JTAG TCK
2. GND
3. JTAG TDO
4. VCCIO JTAG
5. JTAG TMS
6. VCCIO UART
7. UART RX
8. UART TX
9. JTAG TDI
10. GND

The debugger is built around an USB dual core UART from Future technologies (http://www.ftdi.com). Extending the functionallity is possible by using the development environment from FTDI.

For pricing information and orders, please visit OpenCores web shop (link).

If you are a company located in EU we recommend you to contact ORSoC directly via info@orsoc.se to avoid unnecessary costs related to VAT.